1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and more particularly, it relates to a flash memory. The present invention also relates to a driving method thereof.
2. Description of the Related Art
Recently, nonvolatile semiconductor memories, for example, flash memories have been in wide use as storages for electronic devices.
In a NAND flash memory, a plurality of NAND cell units are arranged in a memory cell array. One NAND cell unit is composed of a plurality of memory cells serially connected in a column direction, and select gate transistors connected to one end (source side) and the other (drain side) of the plurality of memory cells. Then, a plurality of NAND cell units are adjacently arranged in a row direction. Further, a plurality of memory cells adjacent to one another in a row direction are connected to one common word line, and a bit line is connected to a drain diffusion layer of the drain side select gate transistor. A potential is applied to the bit line and the word line, such that the writing or reading operation of the memory cell is executed.
As the plurality of memory cells are connected to the common selected one word line, this word line has, in writing, memory cells which are selected and into which data is written (hereinafter referred to as “0” programming cells) and memory cells into which no data should be written (hereinafter referred to as “1” programming cells). Therefore, there has been employed a technique for boosting up channel areas of the “1” programming cells in order to prevent erroneous writing (e.g., refer to U.S. Pat. No. 7,196,933).
In boosting up the channel areas of the memory cells, a precharge potential is first transferred from the bit line to the channel areas of the memory cells. Then, a high potential is applied to selected word lines and nonselected word lines, and the channel areas of the memory cells are boosted up. At this point, if the transferred precharge potential is low, the “1” programming cells are not sufficiently boosted up, leading to an increased possibility of erroneous writing.
The transferred precharge potential is substantially equal to the subtraction of a threshold potential of the select gate transistor from its gate potential. That is, the magnitude of the transferable precharge potential is determined by the gate withstand potential of the drain side select gate transistor of the NAND cell unit.
Furthermore, when there is, between the drain side select gate transistor and the “1” programming cell, a memory cell into which data is already written and which thus has an increased threshold potential, the transferred precharge potential decreases due to this memory cell.
Therefore, the channel areas of the cells not selected for writing are insufficiently boosted up, which might lead to erroneous writing.